In the field of semiconductor memory devices, SRAM devices are generally considered inferior to dynamic random access memory (DRAM) devices in regard to the memory capacity for given area on a chip. However, SRAM memory has been widely used in small-to-medium capacity devices, because of its high processing speed and simplicity of implementation. The SRAM memory cell is largely composed of two flip-flop circuits which include two transmitting transistors, two driving transistors and two load devices (i.e., a resistor or MOS transistor). The stored information is preserved in the SRAM memory cell as the voltage difference between the input and output terminals of the flip-flop, that is, a node-accumulated charge. This charge is supplemented from a power line via the load device. Thus, in contrast to the case with DRAM devices, SRAM memory devices do not require a refresh function.
An SRAM cell may use a depletion-type NMOS transistor as its load device, but this is no longer the common practice, owing to the high power consumption of such load device. Instead, a polycrystalline silicon resistor having high resistance has been widely used, since it consumes less power and can be easily manufactured. However, with the ever-increasing requirements for higher memory capacity, the high resistance value of the polycrystalline silicon resistor reduces the difference between load current and leakage current, which undesirably lowers the manufacturing yield of the memory device. In order to solve this problem, a CMOS-type SRAM cell which adopts a PMOS thin-film transistor (TFT) as the load device is used.
FIG. 1 is a circuit diagram of one full CMOS SRAM cell utilizing PMOS TFTs as the load resistors. The CMOS SRAM cell comprises an NMOS first transmitting transistor T.sub.1 formed in one side of the cell, having a gate connected to a word line and a drain connected to a first bit line; an NMOS second transmitting transistor T.sub.2 formed in the other side of the cell, having a gate connected to the word line and a drain connected to a second bit line; an NMOS first driving transistor T.sub.3 having a drain connected to the source of the first transmitting transistor, a grounded (V.sub.ss) source, and a gate connected to the source of second transmitting transistor T.sub.2 ; an NMOS second driving transistor T.sub.4 having a drain connected to second transmitting transistor T.sub.2, a grounded source, and a gate connected to the source of first transmitting transistor T.sub.1 ; a PMOS first TFT T.sub.5 having a drain connected to the drain of NMOS first driving transistor T.sub.3, a source connected to the power line (V.sub.cc), and a gate connected to the gate of NMOS first driving transistor T.sub.3 and to the source of NMOS second transmitting transistor T.sub.2 ; and a PMOS second TFT T.sub.6 having a drain connected to the drain of NMOS second driving transistor T.sub.4, a source connected to the power line, and a gate connected to the gate of NMOS second is driving transistor T.sub.4 and to the source of NMOS first transmitting transistor T.sub.1.
Here, a polycrystalline silicon layer used as a channel of the PMOS TFT is generally formed to a thin thickness for low current consumption and for stable data retention in the standby state. Also, the power line V.sub.cc is connected at a predetermined point to a metal wiring layer for carrying the power supply of the memory device, and is generally formed from the same conductive layer as the above polycrystalline silicon layer. However, when such a thin polycrystalline silicon layer is used for the power line supplying constant power to the channel of the PMOS TFT and the entire memory cell, it is difficult to connect the power line and the overlying metal wiring layer. That is, when the metal wiring layer is connected to the buried power line via a contact hole, the power line being formed in a thin conductive layer is unavoidably etched during contact hole formation, owing to the step difference between the cell array portion and the periphery circuit portion. This problem will be described in more detail with reference to FIGS. 2A and 2B.
FIG. 2A is a layout diagram showing a conventional method for connecting the power line and the metal wiring layer via a contact hole, and FIG. 2B is a cross-sectional view cut along line 2B-2B' of FIG. 2A. There is horizontal registration between FIGS. 2A and 2B, which are arranged on the same sheet of the drawing.
Referring to FIG. 2A, reference numeral 10 denotes a mask pattern for forming the power line, reference numeral 12 denotes a mask pattern for forming the metal wiring layer, and reference numerals 14 and 14' denote a first contact hole through which the metal wiring layer is connected to the power line and a second contact hole through which the metal wiring layer is connected to the substrate, respectively.
Referring to FIG. 2B, reference numeral 20 denotes a semiconductor substrate, reference numerals 22 and 26 denote first and second insulating layers, reference numeral 24 denotes a power line formed in the cell array portion of the memory device, and reference numerals 28 and 28' denote the etched patterns of the metal wiring layer, present in the cell array and periphery circuit portions, respectively.
According to the above structure, since the first and second contact holes 14 and 14' are generally formed at the same time, i.e., through the same etching process, the power line 24 formed of a very thin layer becomes etched during the formation of the contact holes, owing to the step difference of the portions on which the contact holes are formed, that is, between the cell array portion and the periphery circuit portion. That is, the etching time must be sufficiently long that the contact hole 14' in the periphery circuit portion penetrates both the insulating layers 26 and 28. While the conductive polycrystalline silicon layer 24 retards the concurrent etching of the contact hole 14 sufficiently that it does not penetrate through the insulating layer 28, there is an attendant etching back of the sides of the contact hole 14 where it passes through the conductive polycrystalline silicon layer 24. Thus, metal wiring layer 28 and power line 24 are poorly connected at the time of metal layer deposition for forming the metal wiring layer.
As a method for solving the above problem, the first and second holes may be formed separately. This method, however, overly complicates the manufacturing process.
Another method has been suggested in which the power line and the metal wiring layer are indirectly connected to each other, by first forming a p.sup.+ active layer in the substrate where the contact hole is to be formed. This method will be described with reference to FIGS. 3A and 3B.
FIG. 3A is a layout diagram showing a conventional method for connecting the power line and the metal wiring layer via a p.sup.+ active layer, and FIG. 3B is a cross-sectional view cut along line 3B-3B' of FIG. 3A. There is horizontal registration between FIGS. 3A and 3B, which are arranged on the same sheet of the drawing. In FIGS. 3A and 3B elements similar to those in FIGS. 2A and 2B are denoted by the same reference numerals as in FIGS. 2A and 2B. In FIG. 3A reference numeral 16 denotes a mask pattern for forming a p.sup.+ active layer and reference numerals 15 and 15' denote contact holes for connecting p.sup.+ active layer 16 to the power line 24 and the metal wiring layer 28, respectively; and in FIG. 3B, reference numerals 21 and 27 respectively denote a field oxide layer and the p.sup.+ active layer formed in the substrate surface.
In the structure of FIGS. 3A and 3B, the power line 24 and the metal wiring layer 28 are connected via the p.sup.+ active layer 27. However, additional layout area is required for connecting both contact holes, thereby increasing chip size.